The present invention relates to manufacturing of semiconductor chips, device and structures, and more specifically, to implementing systems and processes to minimize reticle distortions induced by deep trench (DT) stresses through iterative modeling and floor planning of semiconductor devices.
Integrated circuit (IC) design involves the creation of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece of semiconductor, typically silicon. IC design can entail several steps. For example, the IC design can involve creating a functional specification, converting the specification to a register transfer level (RTL) description, and during a physical design, using the RTL to create one or more semiconductor chips.
A floorplan of an IC is a schematic representation of the tentative placement of major functional blocks on the integrated circuit. In a floorplan, the RTL of a semiconductor chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed. In addition, spacing for the objects is determined and conflicts related to available space (cost of the chip), required performance, and compactness of the chip are addressed.